Optimizing Fast Fourier Conversion on FPGA Chip Using Synthetic Code with Verilog Hardware Description Language

  • Pouriya Etezadifar Assistant Professor, Department of Electrical Engineering, Imam Hussein University, Tehran
  • Kazem Ghaffari
Keywords: Verilog hardware, Optimization, Fast Fourier Transform, FPGA, Twiddle Factor, FFT, Radix-2, Good-Thomas, Cooley-Tukey, Rader.

Abstract

One of the important methods of signal analysis is Fourier series and Fourier transform. use the Fourier series to analyze alternating and periodic signals, and to process non-periodic, use Fourier transform. In many applications, they sample the analog signal from the converter and process the required numerical data. Discrete Fourier transform is used to analyze discrete signals and extract its frequency harmonics. Mostly, this algorithm is implemented on software packages using software such as MATLAB, but hardware implementation has the undeniable benefits such as a much higher speed that makes it suitable for real-time processing. FPGA chips are well-suited platforms for implementing signal processing algorithms such as fast Fourier Transform, due to their advantages such as higher performance and flexibility and parallel processing compared to other hardware packages such as microcontrollers or DSP. In this paper, we implement optimized Fast Fourier Transform algorithm by implementing Verilog hardware on FPGA chip.

References

[1] A. Fatima "Designing Simulation of 32 Point FFT Using Radix-2 Algorithm for FPGA ", IOSR Journal of Electrical and Electronics Engineering, Volume 4, Issue 1, Ver 03, Jan 2014.
[2] A. Ilker.Sin. "Fast Fourier Transform", Istanbul, Okan University, 2012.
[3] U. Meyer- Baese, "Digital Signal Processing with Field Programmable Gate Arrays", New York, Springer, 2001-Third Edition.
[4] S. Gupta. "Low Power Implementation of Fast Fourier Transform Processor On FPGA", International journal of Advance Computer Research, Volume 3, Number 4, 2013.
[5] D. Korchemny, E. Cerny, J.Havlicek , S.Dudani, "The Power Of Assertion System Verilog " , New York , Springer, 2010.
[6] K. Satyadurga, P. R Mahidhar, N V G.Prasad., "Design And Simulation Of Floating Point 32 Input Split Radix Algorithm", International Journal Of Electronics and Communication & Instrumentation Engineering Research and Development. Volume-4, Issue- 1, Feb 2014.
[7] S. Banerjee, "Implementation of Fast Fourier Transform on FPGA Using Verilog HDL", Deptt of Electronics & Electrical Communication Indian Institute of Technology Kharagpur, Volume 5, Issue 2, Ver.I, 2005.
[8] B. Usharani, K. Venkateswara rao, "FPGA Implementation Based On 32_Point FFT Using Radix_2 Algorithm", International Journal of VLSI System Design and Communication Systems. Volume-3, Issue- 05, 2015.
Published
2021-09-01
How to Cite
Etezadifar, P., & Ghaffari, K. (2021). Optimizing Fast Fourier Conversion on FPGA Chip Using Synthetic Code with Verilog Hardware Description Language. Majlesi Journal of Mechatronic Systems, 10(3), 13-26. Retrieved from https://ms.majlesi.info/index.php/ms/article/view/496
Section
Articles