A 2GHz 64x64-bit Low-Latency Pipelined Booth Multiplier
Abstract
Today's parallel multipliers generally comprise three main parts: First is Partial Products Generator, which the most common method for this is to use Modified Booth Encoder (MBE) since it reduces the number of rows of an n bit multiplier to n/2+1 as well as executing signed multiplications. The second part is circuits that add Partial Products of equal value vertically to reduce the number of rows created in the first part into two rows. This part is generally done by Compressor or Counter. Finally, the third part is the final adder, which adds up the remaining two rows of the second part and produces the final multiplication outputs. Improvement in each of these 3 main parts can enhance the overall capacity of the multiplier. This paper presents a new high-speed 64x64-bit CMOS 8 stage pipelined Booth multiplier using fast booth encoder/decoder circuits, a new extra row elimination technique and a modified adder aiming to improve the speed of pipelined multiplier. In the proposed design, generation of first 31 bit rows and 32th row have the latency as low as 380 and 420 ps respectively due to optimizations in Booth Encoder/Decoder and first stage circuits. By applying these new architectures, the final adder performs 108-bit addition in only three cycles with high speed (2 GHz). With a 31% increase in the number of transistors and a 41% increase in latency, the multiplying sampling rate is 571% higher than the similar non-pipeline case. Power consumption @ 2GHz and 1.8 power supply is 924 mW. This multiplier is implemented in TSMC 0.18 µ CMOS technology and the results prove the effectiveness of the proposed method.
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